1. Field of the Invention
The present invention relates to an image processing apparatus, printing apparatus and control method in an image processing apparatus. Particularly, the present invention relates to an image processing apparatus, printing apparatus and control method in an image processing apparatus in a data transfer system which transfers image data.
2. Description of the Related Art
As a high-speed serial interface, a PCI Express® interface, which is a succeeding specification of the PCI bus system, has been proposed (see, for example, U.S. Patent Application Publication Nos. 2006/0114918 and 2006/0277344). A PCI Express serial bus has an effect of reducing the hardware cost because the number of signals is smaller than that in a PCI parallel bus. For example, the number of signal lines on a board can be reduced, and the substrate area and connector size can be decreased. PCI Express can simultaneously provide a bandwidth twice or more that of the PCI and thus can meet demands for higher speed and higher performance.
Since PCI Express employs a point to point connection, extension of the system configuration is implemented by providing port extension at a switch and transferring packets.
FIG. 13 is a block diagram exemplifying a data transfer system using PCI Express.
As shown in FIG. 13, this system includes a CPU 200, a root complex 201, a RAM 202, a switch 204, and endpoint devices 206 and 207. The root complex 201 is the top layer of the PCI Express hierarchy. The root complex 201 connects the CPU 200 and RAM 202, and is connected to the endpoint devices 206 and 207 via the switch 204. The root complex 201 includes a GMCH (Graphics Memory Controller Hub) in a computer system. The endpoint devices 206 and 207 assume interface controller devices (for example, Ethernet® controllers), HDD controllers, or the like.
The root complex side of PCI Express is called an upstream, and the endpoint side is called a downstream. A link is established by transmission/reception for initialization according to the PCI Express protocol. A port 204a of the switch 204 is connected to the root complex 201 and called an upstream port. Ports 204b and 204c of the switch 204 are connected to the endpoint devices 206 and 207, respectively, and called downstream ports.
FIG. 14 is a block diagram showing a system configuration when the endpoint device 207 in the configuration shown in FIG. 13 is replaced with an SOC 208 having a CPU, memory controller, and other processing functions. General-purpose CPUs and root complexes used in a computer and the like can be expected to shorten the development period because the cost performance with respect to their total throughput is high and there are an abundance of available standard libraries. However, they tend to consume a large amount of power.
In view of this, when the system is used in the power saving mode, power supply to the CPU 200, root complex 201, and RAM 202 larger in power consumption than the SOC 208 is stopped. Instead, the SOC 208, which incorporates a CPU, controls the system in the power saving mode, greatly reducing power consumption.
However, the system using PCI Express fails in a configuration access without the root complex device, performs neither power control nor initialization, and cannot shift to the power saving mode.